NHR PerfLab Seminar: A RISC-V vector CPU for High-Performance Computing: architecture, platforms and tools to make it happen (December 10, hybrid)
Title: A RISC-V vector CPU for High-Performance Computing: architecture, platforms and tools to make it happen
Speaker: Dr. Filippo Mantovani, Barcelona Supercomputing Center
Date and time: Tuesday, December 10, 2024, 2.00 p.m. CET
Location (hybrid event): Seminar room 2.049 (RRZE, Martensstraße 1, 91058 Erlangen) and Zoom: https://go-nhr.de/perflab-seminar
Abstract
The European Processor Initiative (EPI) is a project dedicated to developing a general-purpose processor and an accelerator, alongside the necessary software layers for their integration into the High Performance Computing (HPC) ecosystem. The Barcelona Supercomputing Center is contributing to the development of a RISC-V-based accelerator targeted at HPC applications, leveraging the RISC-V vector extension.
This talk aims to provide a comprehensive overview of the EPI project, an introduction to RISC-V, and insights into vector supercomputing. Special emphasis will be placed on the RISC-V vector extensions (RVV), with a particular focus on implementations utilizing large vectors. Participants will gain an understanding of how RVV compares with other vector architectures and explore a design approach that utilizes vectors up to 16-kbit wide. Ultimately, the talk aims to present the methodologies, tools, and libraries available for vectorization, while addressing the accompanying challenges and limitations.
Short bio
Filippo Mantovani is an established researcher responsible for the Mobile and embedded-based HPC group at the Barcelona Supercomputing Center (BSC). He graduated in mathematics and holds a Ph.D. in Computer Science from the University of Ferrara, Italy. He has been a scientific associate at the DESY laboratory in Zeuthen, Germany, and the University of Regensburg, Germany, spending most of his scientific career in computational physics and high-performance computing. He brought up and evaluated large high-performance computing systems, contributing to the Janus, QPACE and Mont-Blanc projects. He is involved in the FPGA prototyping tasks of RISC-V-based accelerators within the European Processor Initiative (EPI). Also, he is currently leading the collaboration between BSC and industrial group Etxe-tar for optimizing high-throughput manufacturing systems.
For a list of past and upcoming NHR PerfLab seminar events, see: https://hpc.fau.de/research/nhr-perflab-seminar-series/