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NHR@FAU

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  4. Core-Level Performance Engineering

Core-Level Performance Engineering

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Core-Level Performance Engineering

Course Description

This course covers performance engineering approaches on the CPU core level.

While many developers put a lot of effort into optimizing parallelism and the execution of their applications on a cluster with multiple nodes, they often lose track of the importance of an efficient serial code first.

Even worse, slow serial code tends to scale very well, hiding the fact that resources are wasted. This course conveys the required knowledge to develop a thorough understanding of the interactions between software and hardware on the level of a single CPU and the lowest memory hierarchy, i.e., the level-1 cache. Relevant properties of instruction execution on superscalar out-of-order CPUs are explained in detail, and the role of critical path, loop-carried dependencies, and instruction throughput limits is discussed.

This course covers general computer architecture for x86 and ARM processors, an introduction to (AT&T and AArch64) assembly code, and performance analysis and engineering using the Open Source Architecture Code Analyzer (OSACA) in combination with the Compiler Explorer. Attendees will work with these tools to analyze compiler-generated assembly kernels and assess their performance properties in detail.

Certification

A certificate of participation will be awarded to all participants who actively engage in the course.

Prerequisites

In order to do the hands-on exercises, an up-to-date web browser (e.g., Chrome or Firefox) is required.

Participants should additionally meet the following requirements:

  • A basic understanding of how CPUs work (registers, instruction execution, data transfers) and what “machine instructions” are.
  • A basic understanding of the Roofline model is recommended. You can find some information here (lecture slides) and here (publication by S. Williams).
  • Some experience in using the Compiler Explorer is recommended but not required. You can watch a two-part intro by Matt Godbolt: part 1 part 2

Upcoming Iterations and Additional Courses

You can find dates and registration links for this and other upcoming NHR@FAU courses at https://hpc.fau.de/teaching/tutorials-and-courses/.

Erlangen National High Performance Computing Center (NHR@FAU)
Martensstraße 1
91058 Erlangen
Germany
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