NHR PerfLab Seminar: The MAQAO performance analysis and optimization framework (hybrid)

Picture of a circuit board in green, with the inscription “Perflab Seminar” in front of it and the NHR@FAU logo in the left upper corner.
Image: NHR@FAU

Topic: The MAQAO performance analysis and optimization framework

Speaker: Prof. William Jalby and Dr. Cédric Valensi, University of Versailles

Date and time: Tuesday, March 10, 2026, at 2:00 p.m. CET

Location: Seminar Room 2.049 (RRZE) and online via Zoom

Abstract:

Abstract: MAQAO aims at providing the user with a detailed analysis of an application’s behavior on a given target HPC system at different levels (compiler, memory hierarchy, CPU, …). The ultimate goal is to guide the code developers through the “maze” of possible code optimizations (vectorization, array restructuring, etc.), providing them with a detailed cost/benefit analysis. To achieve this goal, MAQAO combines several techniques, such as measurements and simulation, static and dynamic analysis, sampling and tracing. This variety of techniques allows to increase guidance accuracy while keeping the total analysis cost at a reasonable level.

In this presentation, we will review the main MAQAO functionalities and give examples of detailed analysis of industrial-strength applications.

Short Bios:

William Jalby started his career first at INRIA as a researcher and then joined the University of Illinois (CEDAR project), got appointed Associate Professor at the University of Rennes, and then transferred to the University of Versailles as a Full Professor. His research interests focus on memory system analysis and optimization, compilers, parallelism, and performance analysis methods/tools. Most of his research has been carried out in close collaboration with hardware suppliers (Fujitsu, Bull/atos, ARM, SiPearl, and Intel), tool developers (University of Oregon, CAPS Entreprise), and application developers both from research (CEA, EDF, CNRS) and industry (ESI, MAGMAsoft, Dassault, GNS, RECOM, SAFRAN, CERFACS,…). Since 2004, he is the director of a joint lab (ITACA) between CEA DAM and UVSQ focusing on code optimization techniques. In 2010, he got appointed as CTO of the Exascale Computing Research Lab (a joint HPC laboratory founded by CEA, Intel and UVSQ), and he is leading ECR research activities. He has authored over 100 technical publications in international journals and conferences and directed over 35 PhD theses. He has been coordinating UVSQ participation to three CoEs: POP2, POP3, and TREX.

Cédric Valensi, PhD, has been working as an expert engineer at UVSQ since 2008. His research interests focus on performance analysis and optimization, with particular expertise in the domain of binary rewriting for the purposes of applications instrumentation. Since 2015, he has been the technical lead of the Performance Analysis team at the Li-Parad laboratory, in charge of developing the MAQAO analysis framework. He is also the coordinator of the VI-HPS consortium training program, which aims at teaching application users how to best use performance tools.


For a list of past and upcoming NHR PerfLab seminar events, please see: https://hpc.fau.de/research/nhr-perflab-seminar-series/